FPGA - VHDL - Xilinx ...

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FPGA - VHDL - Xilinx ...

Post  abed.oubari on Thu Feb 25, 2010 12:53 am

You remember the program we made by VHDL - Digital Clock - this program is not really digital clock it's a sort of counter because we can not adjust time!!! so I made some modifications and I added some lines to the program we already made and we can now adjust Seconds, minutes and hours: (I used switchs SW0,SW1 to adjsut minutes and SW2,SW3 to adjust Hours - when you want to adjust put the apropriate switch On and increment or decrement by BTN_North and BTN_South. If you want to Reset Seconds you press BTN_East and if you want to Reset All you press BTN_West ):

--------------------------------- Program ---------------------------------------------------------

----------------------------------------------------------------------------------
-- Digital clock - LCD Display
-- By: Abed OUBARI
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

------------ Library LCD ---------------------------------------------------------
library work;
use Hr_Package.all;


------------------- entity --------------------------------

entity digital_clk is
Port ( clk : in STD_LOGIC;
BTN_north : in STD_LOGIC;
BTN_west : in STD_LOGIC;
BTN_SOUTH : in STD_LOGIC;
BTN_East : in STD_LOGIC;
sw : in std_logic_vector(3 downto 0);
lED : out STD_LOGIC_vector(7 downto 0);

LCD_RS : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
LCD_E : OUT STD_LOGIC;
SF_D : OUT STD_LOGIC_VECTOR(11 DOWNTO Cool;
SF_CE0 : OUT STD_LOGIC);

end digital_clk;


---------------- architecture ---------------------------

architecture Behavioral of digital_clk is
signal INDEX: std_logic_vector(7 downto 0);
signal ASCII: std_logic_vector(7 downto 0);
signal divider: std_logic_vector(31 downto 0);
signal parce1hz: std_logic;
signal cnt1: std_logic_vector(3 downto 0);
signal overflow1: std_logic;
signal cnt2: std_logic_vector(3 downto 0);
signal overflow2: std_logic;
signal cnt3: std_logic_vector(3 downto 0);
signal overflow3: std_logic;
signal cnt4: std_logic_vector(3 downto 0);
signal overflow4: std_logic;
signal cnt5: std_logic_vector(3 downto 0);
signal overflow5: std_logic;
signal cnt6: std_logic_vector(3 downto 0);
signal overflow6: std_logic;
signal Reset: std_logic;
signal tempcnt: std_logic_vector(3 downto 0);

begin
------------ initialize LCD -------------
SF_CE0<='1';
-----------------------------------------

led<= cnt2& cnt1;

Reset <= BTN_west;


--------------------------- LCD DRIVER ---------------------------
pLcd: LCD_DRIVER
port map(Clk => CLK,
rs => LCD_RS,
rw => LCD_RW,
enable => LCD_E,
lcd_data => SF_D,

index => INDEX,
char => ASCII);

----------------- Display Time and name --------------------------
with INDEX select
ASCII <= x"00" when x"00",
x"54" when x"01",
x"49" when x"02",
x"4D" when x"03",
x"45" when x"04",
x"3D" when x"05",
x"00" when x"06",
"0011" & cnt6 when x"07",
"0011" & cnt5 when x"08",
x"3A" when x"09",
"0011" & cnt4 when x"0A",
"0011" & cnt3 when x"0B",
x"3A" when x"0C",
"0011" & cnt2 when x"0D",
"0011" & cnt1 when x"0E",
x"00" when x"40",
x"00" when x"41",
x"00" when x"42",
x"41" when x"43",
x"62" when x"44",
x"65" when x"45",
x"64" when x"46",
x"00" when x"47",
x"4F" when x"48",
x"55" when x"49",
x"42" when x"4A",
x"41" when x"4B",
x"52" when x"4C",
x"49" when x"4D",
x"00" when others;
------------------------------------------------------------------

--------------------------- divider 50MHZ to 1HZ (1seconde) ------
pDiv: process(clk)
begin
if rising_edge(clk) then
if divider<50000000-1 then
divider<=divider+1;
parce1hz<='0';
else
divider<=(others=>'0');
parce1hz<='1';
end if;
end if;
end process;
--------------------------- secondes from 0 to 9 ------------------
pS1: process(clk)
begin
if (reset='1')or(BTN_East='1') then
cnt1<= (others=>'0');
overflow1<='0';
elsif rising_edge(clk)then
overflow1<='0';
if parce1hz='1' then
if (cnt1<9) then
cnt1<=cnt1+1;
else
cnt1<=(others=>'0');
overflow1<='1';
end if;
end if;
end if;
end process;
--------------------------- secondes from 0 to 5 ------------------
pS2: process(clk)
begin
if (reset='1')or(BTN_East='1') then
cnt2<= (others=>'0');
overflow2<='0';
elsif rising_edge(clk)then
overflow2<='0';
if overflow1='1' then
if (cnt2<5) then
cnt2<=cnt2+1;
else
cnt2<=(others=>'0');
overflow2<='1';
end if;
end if;
end if;
end process;
--------------------------- minutes from 0 to 9 ------------------
pm1: process(clk)
begin
if (reset='1') then
cnt3<= (others=>'0');
overflow3<='0';
elsif rising_edge(clk)then
overflow3<='0';

if sw(0)='0' then

if overflow2='1' then
if (cnt3<9) then
cnt3<=cnt3+1;
else
cnt3<=(others=>'0');
overflow3<='1';
end if;
end if;

else
------------------------------------------
if BTN_North='1' then

if parce1hz='1' then

if cnt3<"1001" then

cnt3<=cnt3+1;
else
cnt3<="0000";
end if;
end if;
end if;
------------------------------------------
------------------------------------------
if BTN_south='1' then

if parce1hz='1' then

if cnt3>"0000" then

cnt3<=cnt3-1;
else
cnt3<="1001";
end if;
end if;
end if;
------------------------------------------
end if;
end if;

end process;
--------------------------- minutes from 0 to 5 ------------------
pm2: process(clk)
begin
if (reset='1') then
cnt4<= (others=>'0');
overflow4<='0';
elsif rising_edge(clk)then
overflow4<='0';
if sw(1)='0' then

if overflow3='1' then
if (cnt4<5) then
cnt4<=cnt4+1;
else
cnt4<=(others=>'0');
overflow4<='1';
end if;
end if;

else
------------------------------------------
if BTN_North='1' then

if parce1hz='1' then

if cnt4<"0101" then

cnt4<=cnt4+1;
else
cnt4<="0000";
end if;
end if;
end if;
------------------------------------------
------------------------------------------
if BTN_south='1' then

if parce1hz='1' then

if cnt4>"0000" then

cnt4<=cnt4-1;
else
cnt4<="0101";
end if;
end if;
end if;
------------------------------------------
end if;

end if;
end process;
--------------------------- Hours from 0 to 9 ------------------
ph1: process(clk)
begin
if (reset='1') then
cnt5<= (others=>'0');
overflow5<='0';
elsif rising_edge(clk)then
overflow5<='0';

if sw(2)='0' then
if overflow4='1' then
if (overflow6='0')then
if (cnt5<9)then
cnt5<=cnt5+1;
elsif ((overflow6='1') and (cnt5="0100")) then
reset<='1';
end if;
else
cnt5<=(others=>'0');
overflow5<='0';
end if;
end if;
else
if BTN_North='1' then
if parce1hz='1' then
if cnt6<"0010" then
if cnt5<"1001" then
cnt5<=cnt5+1;
else
cnt5<="0000";

end if;
else
if cnt5<"0011" then
cnt5<=cnt5+1;
else
cnt5<="0000";

end if;
end if;
end if;
end if;
if BTN_South='1' then
if parce1hz='1' then
if cnt6<"0010" then
if cnt5>"0000" then
cnt5<=cnt5-1;
else
cnt5<="1001";

end if;
else
if cnt5>"0000" then
cnt5<=cnt5-1;
else
cnt5<="0011";

end if;
end if;
end if;
end if;
end if;
end if;
end process;
--------------------------- Hours from 0 to 2 ------------------
ph2: process(clk)
begin
if (reset='1') then
cnt6<= (others=>'0');
overflow6<='0';
elsif rising_edge(clk)then

if sw(3)='0' then
overflow6<='0';
if overflow5='1' then
if (cnt6<2) then
cnt6<=cnt6+1;
else
cnt6<=(others=>'0');
overflow6<='1';
end if;
end if;
else
if BTN_North='1' then

if parce1hz='1' then

if cnt5<"0001" then
-------------------------------------
if cnt6<"0010" then
cnt6<=cnt6+1;
else
cnt6<="0000";
end if;

else

if cnt6<"0001" then
cnt6<=cnt6+1;
else
cnt6<="0000";
end if;

end if;
------------------------------------
end if;

end if;
if BTN_South='1' then
if parce1hz='1' then

------------------------------------
if cnt5<"0001" then

if cnt6>"0000" then
cnt6<=cnt6-1;
else
cnt6<="0010";
end if;

else

if cnt6>"0000" then
cnt6<=cnt6-1;
else
cnt6<="0001";
end if;

end if;
-----------------------------------

end if;
end if;
end if;
end if;
end process;

end Behavioral;
------------------------------------------------------------------------------


if someone wants the program send me an email and i will send the source file!
[b][i]


Last edited by abed.oubari on Thu Feb 25, 2010 7:26 am; edited 1 time in total
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Re: FPGA - VHDL - Xilinx ...

Post  abed.oubari on Thu Feb 25, 2010 2:02 am

Admin wrote:[b]
Hi friends let's do some programs! Laughing
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FPGA

Post  SU SU on Thu Feb 25, 2010 12:36 pm

Yes I was also trying to adjust the time by switch. Enenthough I increase and decrease the no by switch, it's so fast and jumb and so I can't adjust the time. So may I ask u to send for me this program. Neutral
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Re: FPGA - VHDL - Xilinx ...

Post  abed.oubari on Thu Feb 25, 2010 1:14 pm

You can copy this program it is correct and it work perfectly make a copy / paste on the program we done with M. Rongen
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Code doesn't work complete

Post  sonca4321 on Sat Jul 31, 2010 2:07 am

I had read it, Code doesn't work complete. It may be changed another in code Hour ( cnt5 + cnt6 ). When minute is 60, Hour not change to 1 ( cnt4 still = 0 ), please help me Fix it, or send me Code work perfectly, Thank you very much. Email : sonca4321@yahoo.com

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Hi!

Post  abed.oubari on Wed Aug 18, 2010 7:20 am

Ok! let me know if it works for you!!??
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The code works fine!!

Post  abed.oubari on Fri Sep 09, 2011 8:44 am

sonca4321 wrote:I had read it, Code doesn't work complete. It may be changed another in code Hour ( cnt5 + cnt6 ). When minute is 60, Hour not change to 1 ( cnt4 still = 0 ), please help me Fix it, or send me Code work perfectly, Thank you very much. Email : sonca4321@yahoo.com


This code works fine but you need to add components to your project! I have theses components if you need the whole project please contact me:

oubari@cnesten.org.ma or abed.oubari@gmail.com

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Re: FPGA - VHDL - Xilinx ...

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