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DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx

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amarece406
yelito004
rehab.hemdan
aparna
pankaj_151988
Akshay Kumar
duytan411
hany_khedr
ssimpson
mahendra.p12
ivandrago21
artachan
kalaria_krushit
shobhit
moulin279
mustafa khalid
viduka
vagusss
abed.oubari
23 posters

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DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx Empty DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx

Post  abed.oubari Fri Sep 09, 2011 8:56 am

Here the code for the ADC -DAC:

---------------------------------------------------------------
-- Spartan-3E Kit: Analog IO Component
-- DAC component: LTC2624 4 channel, 12 bit DAC
-- ADC component: LTC1407 2 channel, 14 bit ADC
-- (c) Abed OUBARI - CNESTEN - Morocco
-- oubari@cnesten.org.ma
--
---------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;
use Hr_Package.all;



-------------------------------------------------------------

entity FunctionGen is
port (
Clk : IN std_logic;
SPI_MOSI : OUT std_logic;
SPI_MISO : in std_logic;
SPI_SCK : OUT std_logic;
DAC_CS : OUT std_logic;
DAC_Clr : OUT std_logic;
AMP_CS : out std_logic;
--AMP_SHDN : OUT std_logic;

AD_CONV : out std_logic;
SPI_SS_B : out std_logic;
SF_CE0 : out std_logic;
FPGA_INIT_B : out std_logic;
----------------------------------
LCD_RS : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
LCD_E : OUT STD_LOGIC;
SF_D : OUT STD_LOGIC_VECTOR(11 DOWNTO 8 );

----------------------------------


----------------------------------
LED: out std_logic_vector(7 downto 0);
SW: in std_logic_vector(3 downto 0);
rot_a: in std_logic;
rot_b: in std_logic;
rot_center: in std_logic;
RS232_DCE_TXD: out std_logic

);
end FunctionGen ;

--------------------------------------

architecture Behavior of FunctionGen is

signal INDEX: std_logic_vector(7 downto 0);
signal ASCII: std_logic_vector(7 downto 0);
--signal BinIN: std_logic_vector (15 downto 0);
--signal BcdOut: std_logic_vector (19 downto 0) );
signal sBCDin: std_logic_vector (15 downto 0);
signal sBCDout: std_logic_vector (19 downto 0);
signal start : std_logic;

signal Rotarydata: std_logic_vector(11 downto 0);
signal bit12 : std_logic_vector (11 downto 0);
signal divider: std_logic_vector(31 downto 0);
signal full: std_logic;
signal khz: std_logic;
signal AdcA_data: std_logic_vector(13 downto 0);

begin

LED<=AdcA_data(13 downto 6);
--LED<=bit12(11 downto 4);
--------------- Initializing ------------------------
SPI_SS_B <= '1';
SF_CE0 <= '1';
FPGA_INIT_B <= '1';
-----------------------------------------------------



sBcdIn <= b"00" & AdcA_data;

pBinBcd: Bin16_Bcd5 port map (Clk => CLK,
BinIN => sBcdIn,
BcdOut => sBcdOut );



--------------------------- LCD DRIVER ---------------------------
pLcd: LCD_DRIVER
port map(Clk => CLK,
rs => LCD_RS,
rw => LCD_RW,
enable => LCD_E,
lcd_data => SF_D,

index => INDEX,
char => ASCII);
---------------- connecting DAC ---------------------
pDAC: S3E_AnalogIO port map
( Clk => Clk,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO,
SPI_SCK => SPI_SCK,
DAC_CS => DAC_CS,
DAC_Clr =>DAC_Clr,
AMP_CS => AMP_CS,
AD_CONV => AD_CONV,
-- locals
--TickAnalogIO => open,
Dac_A => bit12,
--Dac_B => not bit12, --open,
--Dac_C => open,
Dac_D => Rotarydata,

Adc_A => AdcA_Data
--Adc_B => open

);

cRot: Rotary_Counter
generic map (bits => 12)
Port map (clk => clk,
Rot_a => Rot_a,
Rot_b => Rot_b,
Rot_center => Rot_center,
COUNTER => Rotarydata
);

cSerial: Comp_RS232_TX
Port map
(clk => clk,
sDout => RS232_DCE_TXD,
Data => AdcA_data(13 downto 6),
start => Khz
);


------------------ 1Khz counter ---------------------
pDiv: process(clk)
begin
if rising_edge(clk) then
if divider<100000 then ------ 500 hz

divider<= divider+1;
khz<='0';
else
divider<=(others=>'0');
khz<='1';
end if;
end if;
end process;
-----------------------------------------------------
---------------- 12 bit counter ---------------------
p12bit: process(clk)
begin

if rising_edge(clk) then
if khz='1' then
if full='0' then
bit12 <= bit12 + sw; ---- if +sw put x"ff0"
if bit12 > x"ff0" then
full<='1';
end if;
end if;
if full='1' then
bit12<= bit12 - sw; ---- if -sw put x"00F"
if bit12 < x"00f" then
full<='0';
end if;
end if;

end if;
end if;
end process;
------------------------------------------------------
------------ initialize LCD -------------
SF_CE0<='1';
-----------------------------------------
----------------- Display Time and name --------------
with INDEX select
ASCII <= x"00" when x"00",
x"41" when x"01",
x"44" when x"02",
x"43" when x"03",
x"3D" when x"04",
x"00" when x"05",
x"00" when x"06",
x"3" & sBCDout(19 downto 16) when x"07",
x"3" & sBCDout(15 downto 12) when x"08",
x"3" & sBCDout(11 downto 8 ) when x"09",
x"3" & sBCDout(7 downto 4) when x"0A",
x"3" & sBCDout(3 downto 0) when x"0B",
x"00" when others;
------------------------------------------------------------------
end Behavior;

to download the project please click here
https://rapidshare.com/files/2030142705/DAC_VHDL.rar


Last edited by abed.oubari on Fri Mar 08, 2013 3:40 am; edited 1 time in total
abed.oubari
abed.oubari
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Post  vagusss Mon Apr 09, 2012 8:41 am

Hi ,

I'm trying to design an oscilloscope on my Spartan 3e and I need your whole working project file .


Pease contact me as soon as possible.

o.elbir(at)gmail.com

Thank you in advance.

vagusss

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Post  abed.oubari Tue Apr 10, 2012 4:36 am

Please check you email I sent you the hole project...!
Abed.

Laughing
abed.oubari
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Post  viduka Sat Apr 14, 2012 11:40 pm

Hi. can u send to my email too? vicky.dwi.k@gmail.com

if you have picture when u run this program can u send it to me too.. im very appreciate it.. Very Happy

viduka

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Post  abed.oubari Tue Apr 17, 2012 7:45 am

I sent the hole program to you please check you email....!
abed.oubari
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Post  mustafa khalid Tue Apr 24, 2012 1:08 am

i have just contact you by e-mail ,and i follow your registration tasks to get your project

I need your whole working project file . Pease send it to me as soon as possible on my e-mail.



thanQ

mustafa khalid

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Post  moulin279 Fri May 11, 2012 7:56 am

Hello,

I currently designing a project using SPARTAN 3E starter kit and i needed both ADC-DAC running on FPGA in order to test my project.

Could you send me your whole working project?

Thank you in advance!

moulin279

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Post  moulin279 Mon May 28, 2012 12:25 pm

Good afternoon,

I've been trying to utilize this vhdl description for DAC - ADC but it seems not to work... Is there any complementary material about how it works?

Thank you in advance!

moulin279

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Post  abed.oubari Tue May 29, 2012 2:57 am

Hi Mr. MOULIN,

This program work fine! when you open the project it will ask you for additional components, the components are in the same folder "S3E_Components_Packages" browse them and it will works well.

Please try and tell me if it works fine for you.
Smile

abed.oubari
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Post  shobhit Mon Jun 11, 2012 8:15 am

Hello,

I currently working on a project using Xilinx SPARTAN 3E starter kit which involves the use of the onboard ADC-DAC modules on the FPGA.

Could you please send me your whole working project on shobhit6993[at]yahoo.in ?

Thank you very much in advance!





shobhit

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Post  kalaria_krushit Fri Sep 28, 2012 4:03 am

hi,

can you please sent me the full project it will be really helpful to me.

thank you.

kalaria_krushit

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Post  kalaria_krushit Fri Sep 28, 2012 4:17 am

hi,

my email id is kalaria13[at]gmail.com

thanks
kalaria krushit

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Post  kalaria_krushit Fri Sep 28, 2012 4:30 am

hi,

i have to configure only DAC for my project, so can you send me project which has used only DAC.

thanks.

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Post  artachan Sun Sep 30, 2012 3:58 pm

dear Mr. Oubari. i am at my last bachelor project and using spartan 3e. may i get the source code of adc at my mail. artachan@gmail.com. thx u for help and replied. (i'm sorry for my bad english)

artachan

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Post  kalaria_krushit Mon Oct 01, 2012 1:06 am

hi,

can you send me some details of the project that you send me? It would be easy for me to understand what actually your project is and also helpful to understand syntax of the VHDL code. My email-id is kalaria13[at]gmail.com

thanks


kalaria_krushit

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Post  kalaria_krushit Mon Oct 01, 2012 1:08 am

hi,

can you send me some details of your project so that i can understand the syntax of the VHDL code. My email-id is kalaria13[at]gmail.com.

thanks

kalaria_krushit

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DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx Empty May i get the whole project of adc spartan 3 e

Post  artachan Wed Oct 03, 2012 9:19 pm

Dear mr. oubari. may i get the whole project of adc spartan 3 e for my last bachelor project ar artachan@gmail.com. thx u for replied

best regards

arta

artachan

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Post  ivandrago21 Wed Oct 24, 2012 2:41 pm

hi Mr. Oubari i´m a student and i need to use the ADC of the spartan 3E for a project, can you send me the whole work, thank you soo mucho for the support

ivandrago21

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Post  mahendra.p12 Thu Oct 25, 2012 6:27 am

thanks a lot ...your code really works fine..got a good way to use resources on board..
thanks a lot

mahendra.p12

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Post  ssimpson Wed Nov 28, 2012 12:44 pm

Hello,

I currently designing a project using SPARTAN 3E starter kit and i needed both ADC-DAC running on FPGA in order to test my project.

Could you send me your whole working project?

Thank you in advance!.
Stuart








ssimpson

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Post  hany_khedr Fri Jan 18, 2013 1:12 pm

Hello,

currently, I am working to design a project using SPARTAN 3E starter kit and I need ADC-DAC running on FPGA in order to test my project.

I am wounder, if you send me your whole working project.
Thank you in advance!.

Hany Khedr

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DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx Empty Please check your email...

Post  abed.oubari Tue Jan 22, 2013 4:53 am

hany_khedr wrote:Hello,

currently, I am working to design a project using SPARTAN 3E starter kit and I need ADC-DAC running on FPGA in order to test my project.

I am wounder, if you send me your whole working project.
Thank you in advance!.

Hany Khedr


I sent you the code .... please check your email... Cool
abed.oubari
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Post  duytan411 Sat Feb 02, 2013 6:32 pm

Hi Oubari,
I'm doing my project to design a oscilloscope on Altera De2 Board, I'm stucking at the overview of the problem.
Can you send me your project? I'll be a good help for me.
Thanks,
Tand

duytan411

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Post  Akshay Kumar Mon Feb 11, 2013 7:28 am

Hi sir,
i need this whole project ADC-DAC, as i am doing it as an academic project please send the whole project as soon as possible its urgent my mail id is "akshaykumar.kallimani@gmail.com

Akshay Kumar

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Post  pankaj_151988 Wed Mar 06, 2013 5:00 am

i am working on fpga implementation of mppt algoritjm for pv system. i need adc and dac for taking analog voltages and current into fpga .please send me code for adc and dac for sparten 3e.

pankaj_151988

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