DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
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amarece406
yelito004
rehab.hemdan
aparna
pankaj_151988
Akshay Kumar
duytan411
hany_khedr
ssimpson
mahendra.p12
ivandrago21
artachan
kalaria_krushit
shobhit
moulin279
mustafa khalid
viduka
vagusss
abed.oubari
23 posters
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DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
Here the code for the ADC -DAC:
---------------------------------------------------------------
-- Spartan-3E Kit: Analog IO Component
-- DAC component: LTC2624 4 channel, 12 bit DAC
-- ADC component: LTC1407 2 channel, 14 bit ADC
-- (c) Abed OUBARI - CNESTEN - Morocco
-- oubari@cnesten.org.ma
--
---------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use Hr_Package.all;
-------------------------------------------------------------
entity FunctionGen is
port (
Clk : IN std_logic;
SPI_MOSI : OUT std_logic;
SPI_MISO : in std_logic;
SPI_SCK : OUT std_logic;
DAC_CS : OUT std_logic;
DAC_Clr : OUT std_logic;
AMP_CS : out std_logic;
--AMP_SHDN : OUT std_logic;
AD_CONV : out std_logic;
SPI_SS_B : out std_logic;
SF_CE0 : out std_logic;
FPGA_INIT_B : out std_logic;
----------------------------------
LCD_RS : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
LCD_E : OUT STD_LOGIC;
SF_D : OUT STD_LOGIC_VECTOR(11 DOWNTO 8 );
----------------------------------
----------------------------------
LED: out std_logic_vector(7 downto 0);
SW: in std_logic_vector(3 downto 0);
rot_a: in std_logic;
rot_b: in std_logic;
rot_center: in std_logic;
RS232_DCE_TXD: out std_logic
);
end FunctionGen ;
--------------------------------------
architecture Behavior of FunctionGen is
signal INDEX: std_logic_vector(7 downto 0);
signal ASCII: std_logic_vector(7 downto 0);
--signal BinIN: std_logic_vector (15 downto 0);
--signal BcdOut: std_logic_vector (19 downto 0) );
signal sBCDin: std_logic_vector (15 downto 0);
signal sBCDout: std_logic_vector (19 downto 0);
signal start : std_logic;
signal Rotarydata: std_logic_vector(11 downto 0);
signal bit12 : std_logic_vector (11 downto 0);
signal divider: std_logic_vector(31 downto 0);
signal full: std_logic;
signal khz: std_logic;
signal AdcA_data: std_logic_vector(13 downto 0);
begin
LED<=AdcA_data(13 downto 6);
--LED<=bit12(11 downto 4);
--------------- Initializing ------------------------
SPI_SS_B <= '1';
SF_CE0 <= '1';
FPGA_INIT_B <= '1';
-----------------------------------------------------
sBcdIn <= b"00" & AdcA_data;
pBinBcd: Bin16_Bcd5 port map (Clk => CLK,
BinIN => sBcdIn,
BcdOut => sBcdOut );
--------------------------- LCD DRIVER ---------------------------
pLcd: LCD_DRIVER
port map(Clk => CLK,
rs => LCD_RS,
rw => LCD_RW,
enable => LCD_E,
lcd_data => SF_D,
index => INDEX,
char => ASCII);
---------------- connecting DAC ---------------------
pDAC: S3E_AnalogIO port map
( Clk => Clk,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO,
SPI_SCK => SPI_SCK,
DAC_CS => DAC_CS,
DAC_Clr =>DAC_Clr,
AMP_CS => AMP_CS,
AD_CONV => AD_CONV,
-- locals
--TickAnalogIO => open,
Dac_A => bit12,
--Dac_B => not bit12, --open,
--Dac_C => open,
Dac_D => Rotarydata,
Adc_A => AdcA_Data
--Adc_B => open
);
cRot: Rotary_Counter
generic map (bits => 12)
Port map (clk => clk,
Rot_a => Rot_a,
Rot_b => Rot_b,
Rot_center => Rot_center,
COUNTER => Rotarydata
);
cSerial: Comp_RS232_TX
Port map
(clk => clk,
sDout => RS232_DCE_TXD,
Data => AdcA_data(13 downto 6),
start => Khz
);
------------------ 1Khz counter ---------------------
pDiv: process(clk)
begin
if rising_edge(clk) then
if divider<100000 then ------ 500 hz
divider<= divider+1;
khz<='0';
else
divider<=(others=>'0');
khz<='1';
end if;
end if;
end process;
-----------------------------------------------------
---------------- 12 bit counter ---------------------
p12bit: process(clk)
begin
if rising_edge(clk) then
if khz='1' then
if full='0' then
bit12 <= bit12 + sw; ---- if +sw put x"ff0"
if bit12 > x"ff0" then
full<='1';
end if;
end if;
if full='1' then
bit12<= bit12 - sw; ---- if -sw put x"00F"
if bit12 < x"00f" then
full<='0';
end if;
end if;
end if;
end if;
end process;
------------------------------------------------------
------------ initialize LCD -------------
SF_CE0<='1';
-----------------------------------------
----------------- Display Time and name --------------
with INDEX select
ASCII <= x"00" when x"00",
x"41" when x"01",
x"44" when x"02",
x"43" when x"03",
x"3D" when x"04",
x"00" when x"05",
x"00" when x"06",
x"3" & sBCDout(19 downto 16) when x"07",
x"3" & sBCDout(15 downto 12) when x"08",
x"3" & sBCDout(11 downto 8 ) when x"09",
x"3" & sBCDout(7 downto 4) when x"0A",
x"3" & sBCDout(3 downto 0) when x"0B",
x"00" when others;
------------------------------------------------------------------
end Behavior;
to download the project please click here
https://rapidshare.com/files/2030142705/DAC_VHDL.rar
---------------------------------------------------------------
-- Spartan-3E Kit: Analog IO Component
-- DAC component: LTC2624 4 channel, 12 bit DAC
-- ADC component: LTC1407 2 channel, 14 bit ADC
-- (c) Abed OUBARI - CNESTEN - Morocco
-- oubari@cnesten.org.ma
--
---------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use Hr_Package.all;
-------------------------------------------------------------
entity FunctionGen is
port (
Clk : IN std_logic;
SPI_MOSI : OUT std_logic;
SPI_MISO : in std_logic;
SPI_SCK : OUT std_logic;
DAC_CS : OUT std_logic;
DAC_Clr : OUT std_logic;
AMP_CS : out std_logic;
--AMP_SHDN : OUT std_logic;
AD_CONV : out std_logic;
SPI_SS_B : out std_logic;
SF_CE0 : out std_logic;
FPGA_INIT_B : out std_logic;
----------------------------------
LCD_RS : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
LCD_E : OUT STD_LOGIC;
SF_D : OUT STD_LOGIC_VECTOR(11 DOWNTO 8 );
----------------------------------
----------------------------------
LED: out std_logic_vector(7 downto 0);
SW: in std_logic_vector(3 downto 0);
rot_a: in std_logic;
rot_b: in std_logic;
rot_center: in std_logic;
RS232_DCE_TXD: out std_logic
);
end FunctionGen ;
--------------------------------------
architecture Behavior of FunctionGen is
signal INDEX: std_logic_vector(7 downto 0);
signal ASCII: std_logic_vector(7 downto 0);
--signal BinIN: std_logic_vector (15 downto 0);
--signal BcdOut: std_logic_vector (19 downto 0) );
signal sBCDin: std_logic_vector (15 downto 0);
signal sBCDout: std_logic_vector (19 downto 0);
signal start : std_logic;
signal Rotarydata: std_logic_vector(11 downto 0);
signal bit12 : std_logic_vector (11 downto 0);
signal divider: std_logic_vector(31 downto 0);
signal full: std_logic;
signal khz: std_logic;
signal AdcA_data: std_logic_vector(13 downto 0);
begin
LED<=AdcA_data(13 downto 6);
--LED<=bit12(11 downto 4);
--------------- Initializing ------------------------
SPI_SS_B <= '1';
SF_CE0 <= '1';
FPGA_INIT_B <= '1';
-----------------------------------------------------
sBcdIn <= b"00" & AdcA_data;
pBinBcd: Bin16_Bcd5 port map (Clk => CLK,
BinIN => sBcdIn,
BcdOut => sBcdOut );
--------------------------- LCD DRIVER ---------------------------
pLcd: LCD_DRIVER
port map(Clk => CLK,
rs => LCD_RS,
rw => LCD_RW,
enable => LCD_E,
lcd_data => SF_D,
index => INDEX,
char => ASCII);
---------------- connecting DAC ---------------------
pDAC: S3E_AnalogIO port map
( Clk => Clk,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO,
SPI_SCK => SPI_SCK,
DAC_CS => DAC_CS,
DAC_Clr =>DAC_Clr,
AMP_CS => AMP_CS,
AD_CONV => AD_CONV,
-- locals
--TickAnalogIO => open,
Dac_A => bit12,
--Dac_B => not bit12, --open,
--Dac_C => open,
Dac_D => Rotarydata,
Adc_A => AdcA_Data
--Adc_B => open
);
cRot: Rotary_Counter
generic map (bits => 12)
Port map (clk => clk,
Rot_a => Rot_a,
Rot_b => Rot_b,
Rot_center => Rot_center,
COUNTER => Rotarydata
);
cSerial: Comp_RS232_TX
Port map
(clk => clk,
sDout => RS232_DCE_TXD,
Data => AdcA_data(13 downto 6),
start => Khz
);
------------------ 1Khz counter ---------------------
pDiv: process(clk)
begin
if rising_edge(clk) then
if divider<100000 then ------ 500 hz
divider<= divider+1;
khz<='0';
else
divider<=(others=>'0');
khz<='1';
end if;
end if;
end process;
-----------------------------------------------------
---------------- 12 bit counter ---------------------
p12bit: process(clk)
begin
if rising_edge(clk) then
if khz='1' then
if full='0' then
bit12 <= bit12 + sw; ---- if +sw put x"ff0"
if bit12 > x"ff0" then
full<='1';
end if;
end if;
if full='1' then
bit12<= bit12 - sw; ---- if -sw put x"00F"
if bit12 < x"00f" then
full<='0';
end if;
end if;
end if;
end if;
end process;
------------------------------------------------------
------------ initialize LCD -------------
SF_CE0<='1';
-----------------------------------------
----------------- Display Time and name --------------
with INDEX select
ASCII <= x"00" when x"00",
x"41" when x"01",
x"44" when x"02",
x"43" when x"03",
x"3D" when x"04",
x"00" when x"05",
x"00" when x"06",
x"3" & sBCDout(19 downto 16) when x"07",
x"3" & sBCDout(15 downto 12) when x"08",
x"3" & sBCDout(11 downto 8 ) when x"09",
x"3" & sBCDout(7 downto 4) when x"0A",
x"3" & sBCDout(3 downto 0) when x"0B",
x"00" when others;
------------------------------------------------------------------
end Behavior;
to download the project please click here
https://rapidshare.com/files/2030142705/DAC_VHDL.rar
Last edited by abed.oubari on Fri Mar 08, 2013 3:40 am; edited 1 time in total
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
Hi ,
I'm trying to design an oscilloscope on my Spartan 3e and I need your whole working project file .
Pease contact me as soon as possible.
o.elbir(at)gmail.com
Thank you in advance.
I'm trying to design an oscilloscope on my Spartan 3e and I need your whole working project file .
Pease contact me as soon as possible.
o.elbir(at)gmail.com
Thank you in advance.
vagusss- Posts : 1
Join date : 2012-04-09
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
Hi. can u send to my email too? vicky.dwi.k@gmail.com
if you have picture when u run this program can u send it to me too.. im very appreciate it..
if you have picture when u run this program can u send it to me too.. im very appreciate it..
viduka- Posts : 2
Join date : 2012-02-17
ADC/DAC project on SPARTAN3E
i have just contact you by e-mail ,and i follow your registration tasks to get your project
I need your whole working project file . Pease send it to me as soon as possible on my e-mail.
thanQ
I need your whole working project file . Pease send it to me as soon as possible on my e-mail.
thanQ
mustafa khalid- Posts : 1
Join date : 2012-04-24
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
Hello,
I currently designing a project using SPARTAN 3E starter kit and i needed both ADC-DAC running on FPGA in order to test my project.
Could you send me your whole working project?
Thank you in advance!
I currently designing a project using SPARTAN 3E starter kit and i needed both ADC-DAC running on FPGA in order to test my project.
Could you send me your whole working project?
Thank you in advance!
moulin279- Posts : 2
Join date : 2012-05-11
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
Good afternoon,
I've been trying to utilize this vhdl description for DAC - ADC but it seems not to work... Is there any complementary material about how it works?
Thank you in advance!
I've been trying to utilize this vhdl description for DAC - ADC but it seems not to work... Is there any complementary material about how it works?
Thank you in advance!
moulin279- Posts : 2
Join date : 2012-05-11
It works fine...!
Hi Mr. MOULIN,
This program work fine! when you open the project it will ask you for additional components, the components are in the same folder "S3E_Components_Packages" browse them and it will works well.
Please try and tell me if it works fine for you.
This program work fine! when you open the project it will ask you for additional components, the components are in the same folder "S3E_Components_Packages" browse them and it will works well.
Please try and tell me if it works fine for you.
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
Hello,
I currently working on a project using Xilinx SPARTAN 3E starter kit which involves the use of the onboard ADC-DAC modules on the FPGA.
Could you please send me your whole working project on shobhit6993[at]yahoo.in ?
Thank you very much in advance!
I currently working on a project using Xilinx SPARTAN 3E starter kit which involves the use of the onboard ADC-DAC modules on the FPGA.
Could you please send me your whole working project on shobhit6993[at]yahoo.in ?
Thank you very much in advance!
shobhit- Posts : 1
Join date : 2012-06-11
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
hi,
can you please sent me the full project it will be really helpful to me.
thank you.
can you please sent me the full project it will be really helpful to me.
thank you.
kalaria_krushit- Posts : 5
Join date : 2012-09-28
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
hi,
my email id is kalaria13[at]gmail.com
thanks
kalaria krushit
my email id is kalaria13[at]gmail.com
thanks
kalaria krushit
kalaria_krushit- Posts : 5
Join date : 2012-09-28
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
hi,
i have to configure only DAC for my project, so can you send me project which has used only DAC.
thanks.
i have to configure only DAC for my project, so can you send me project which has used only DAC.
thanks.
kalaria_krushit- Posts : 5
Join date : 2012-09-28
may i get the all source code of adc
dear Mr. Oubari. i am at my last bachelor project and using spartan 3e. may i get the source code of adc at my mail. artachan@gmail.com. thx u for help and replied. (i'm sorry for my bad english)
artachan- Posts : 2
Join date : 2012-09-22
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
hi,
can you send me some details of the project that you send me? It would be easy for me to understand what actually your project is and also helpful to understand syntax of the VHDL code. My email-id is kalaria13[at]gmail.com
thanks
can you send me some details of the project that you send me? It would be easy for me to understand what actually your project is and also helpful to understand syntax of the VHDL code. My email-id is kalaria13[at]gmail.com
thanks
kalaria_krushit- Posts : 5
Join date : 2012-09-28
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
hi,
can you send me some details of your project so that i can understand the syntax of the VHDL code. My email-id is kalaria13[at]gmail.com.
thanks
can you send me some details of your project so that i can understand the syntax of the VHDL code. My email-id is kalaria13[at]gmail.com.
thanks
kalaria_krushit- Posts : 5
Join date : 2012-09-28
May i get the whole project of adc spartan 3 e
Dear mr. oubari. may i get the whole project of adc spartan 3 e for my last bachelor project ar artachan@gmail.com. thx u for replied
best regards
arta
best regards
arta
artachan- Posts : 2
Join date : 2012-09-22
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
hi Mr. Oubari i´m a student and i need to use the ADC of the spartan 3E for a project, can you send me the whole work, thank you soo mucho for the support
ivandrago21- Posts : 1
Join date : 2012-10-24
adc on sparton 3 e
thanks a lot ...your code really works fine..got a good way to use resources on board..
thanks a lot
thanks a lot
mahendra.p12- Posts : 1
Join date : 2012-10-16
adc dac code
Hello,
I currently designing a project using SPARTAN 3E starter kit and i needed both ADC-DAC running on FPGA in order to test my project.
Could you send me your whole working project?
Thank you in advance!.
Stuart
I currently designing a project using SPARTAN 3E starter kit and i needed both ADC-DAC running on FPGA in order to test my project.
Could you send me your whole working project?
Thank you in advance!.
Stuart
ssimpson- Posts : 1
Join date : 2012-11-28
adc on sparton3e starter kit
Hello,
currently, I am working to design a project using SPARTAN 3E starter kit and I need ADC-DAC running on FPGA in order to test my project.
I am wounder, if you send me your whole working project.
Thank you in advance!.
Hany Khedr
currently, I am working to design a project using SPARTAN 3E starter kit and I need ADC-DAC running on FPGA in order to test my project.
I am wounder, if you send me your whole working project.
Thank you in advance!.
Hany Khedr
hany_khedr- Posts : 1
Join date : 2013-01-18
Please check your email...
hany_khedr wrote:Hello,
currently, I am working to design a project using SPARTAN 3E starter kit and I need ADC-DAC running on FPGA in order to test my project.
I am wounder, if you send me your whole working project.
Thank you in advance!.
Hany Khedr
I sent you the code .... please check your email...
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
Hi Oubari,
I'm doing my project to design a oscilloscope on Altera De2 Board, I'm stucking at the overview of the problem.
Can you send me your project? I'll be a good help for me.
Thanks,
Tand
I'm doing my project to design a oscilloscope on Altera De2 Board, I'm stucking at the overview of the problem.
Can you send me your project? I'll be a good help for me.
Thanks,
Tand
duytan411- Posts : 1
Join date : 2013-02-02
ADC-DAC
Hi sir,
i need this whole project ADC-DAC, as i am doing it as an academic project please send the whole project as soon as possible its urgent my mail id is "akshaykumar.kallimani@gmail.com
i need this whole project ADC-DAC, as i am doing it as an academic project please send the whole project as soon as possible its urgent my mail id is "akshaykumar.kallimani@gmail.com
Akshay Kumar- Posts : 1
Join date : 2013-01-22
adc -dac
i am working on fpga implementation of mppt algoritjm for pv system. i need adc and dac for taking analog voltages and current into fpga .please send me code for adc and dac for sparten 3e.
pankaj_151988- Posts : 1
Join date : 2013-03-06
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