DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
+19
amarece406
yelito004
rehab.hemdan
aparna
pankaj_151988
Akshay Kumar
duytan411
hany_khedr
ssimpson
mahendra.p12
ivandrago21
artachan
kalaria_krushit
shobhit
moulin279
mustafa khalid
viduka
vagusss
abed.oubari
23 posters
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Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
artachan wrote:Dear mr. oubari. may i get the whole project of adc spartan 3 e for my last bachelor project ar artachan@gmail.com. thx u for replied
best regards
arta
please download it from here:
https://rapidshare.com/files/2030142705/DAC_VHDL.rar
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
please send the full workin code to my email address also..urgent!!
aparna- Posts : 1
Join date : 2013-03-08
DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
Hi OUBARI
thanks for sending your project
I try to use only ADC-DAC from your code
but I can not understand how this states work
when S18 => Dac_CS <= '0'; -- LOOP: set Data
SPI_SCK <= '0';
SPI_MOSI <= sData(31);
i := i + 1;
if (i>1) then
bitnr := bitnr +1;
sData <= sData (30 downto 0) & '0';
i := 0;
sDacState <= S19;
end if;
when S19 => SPI_SCK <= '1';
i := i + 1;
if (i>1) then
if (bitnr < then -- Set Clock
i := 0;
sDacState <= S18;
else
i := 0;
sDacState <= S20;
end if;
end if;
when S20 => AMP_CS <= '1'; -- OK
SPI_SCK <= '0';
i := i + 1;
if (i>1) then
i := 0;
sDacState <= S21;
end if;
where i will be never i>1
thanks for sending your project
I try to use only ADC-DAC from your code
but I can not understand how this states work
when S18 => Dac_CS <= '0'; -- LOOP: set Data
SPI_SCK <= '0';
SPI_MOSI <= sData(31);
i := i + 1;
if (i>1) then
bitnr := bitnr +1;
sData <= sData (30 downto 0) & '0';
i := 0;
sDacState <= S19;
end if;
when S19 => SPI_SCK <= '1';
i := i + 1;
if (i>1) then
if (bitnr < then -- Set Clock
i := 0;
sDacState <= S18;
else
i := 0;
sDacState <= S20;
end if;
end if;
when S20 => AMP_CS <= '1'; -- OK
SPI_SCK <= '0';
i := i + 1;
if (i>1) then
i := 0;
sDacState <= S21;
end if;
where i will be never i>1
rehab.hemdan- Posts : 2
Join date : 2013-03-30
thank you for your code
Hello,
Could you please send me your whole working project on tlatel.yelito[at]gmail.com ?
i'll try to use only the DAC part of it.
thank u very much
yelito004- Posts : 1
Join date : 2013-04-03
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
yelito004 wrote:
Hello,
Could you please send me your whole working project on tlatel.yelito[at]gmail.com ?
i'll try to use only the DAC part of it.
thank u very much
---------------------------
I send you the code
rehab.hemdan- Posts : 2
Join date : 2013-03-30
Please donwnload it from here!!!
rehab.hemdan wrote:yelito004 wrote:
Hello,
Could you please send me your whole working project on tlatel.yelito[at]gmail.com ?
i'll try to use only the DAC part of it.
thank u very much
---------------------------
I send you the code
rapidshare.com rapidshare.comDAC_VHDL.rar
download full ADC-DAC code
download it from here:
https://rapidshare.com/files/2030142705/DAC_VHDL.rar
https://rapidshare.com/files/2030142705/DAC_VHDL.rar
Download full DAC ADC code ...!
Download it from here:
https://rapidshare.com/files/2030142705/DAC_VHDL.rar
https://rapidshare.com/files/2030142705/DAC_VHDL.rar
PLEASE HELP IN INTERFACING ADC TO SPARTAN 3E FPGA
HELLO ADMIN,
I integrated the VHDL codes of both onboard ADC and DAC interface to spartan 3E FPGA. its working for a DC signal but not for an AC (sinusoidal )signal. for an AC input signal the output is coming with a frequency less than the input applied even for a triangular and square wave. can anyone solve this problem pls reply me
I integrated the VHDL codes of both onboard ADC and DAC interface to spartan 3E FPGA. its working for a DC signal but not for an AC (sinusoidal )signal. for an AC input signal the output is coming with a frequency less than the input applied even for a triangular and square wave. can anyone solve this problem pls reply me
Last edited by amarece406 on Sun Jun 09, 2013 10:39 pm; edited 1 time in total (Reason for editing : i had done 80% of the work i'm struck with few problems)
amarece406- Posts : 1
Join date : 2013-06-04
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
can you sent me your whole project to jhonweslyb[at]gmail.com
thank you
thank you
jhonweslybangun- Posts : 1
Join date : 2013-06-07
hii
please i need the code with the package, i need the ADC part, i already wrote the LCD display model but i have a problem with ADC code.
my e-mail is (nona71183 ( at )yahoo.com)
thank u in advanced
my e-mail is (nona71183 ( at )yahoo.com)
thank u in advanced
rose_spartan- Posts : 1
Join date : 2013-06-17
sir ,me too send the adc dac code entire project file to mail.mail id:sabariharish3@gmail.com
abed.oubari wrote:I sent the hole program to you please check you email....!
sabariharish- Posts : 1
Join date : 2014-04-06
Re: DAC -ADC --->FPGA-VHDL -SPARTAN 3E - Xilinx
hey my friend, i am trying hard to complete my project can i get code for "data transfer between two spartan 3E kits using xilinx software" you can mail to harishbandaru93 its an gmail account. please
HARISH BANDARU- Posts : 1
Join date : 2014-11-17
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