GFT2009_2010 - 

Here the code for the ADC -DAC:

---------------------------------------------------------------
-- Spartan-3E Kit: Analog IO Component
-- DAC component: LTC2624 4 channel, 12 bit DAC
-- ADC component: LTC1407 2 channel, 14 bit ADC
-- (c) Abed OUBARI - CNESTEN - Morocco
-- oubari@cnesten.org.ma
--
---------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library work;
use Hr_Package.all;



-------------------------------------------------------------

entity FunctionGen is
port (
Clk : IN std_logic;
SPI_MOSI : OUT std_logic;
SPI_MISO : in std_logic;
SPI_SCK : OUT std_logic;
DAC_CS : OUT std_logic;
DAC_Clr : OUT std_logic;
AMP_CS : out std_logic;
--AMP_SHDN : OUT std_logic;

AD_CONV : out std_logic;
SPI_SS_B : out std_logic;
SF_CE0 : out std_logic;
FPGA_INIT_B : out std_logic;
----------------------------------
LCD_RS : OUT STD_LOGIC;
LCD_RW : OUT STD_LOGIC;
LCD_E : OUT STD_LOGIC;
SF_D : OUT STD_LOGIC_VECTOR(11 DOWNTO 8 );

----------------------------------


----------------------------------
LED: out std_logic_vector(7 downto 0);
SW: in std_logic_vector(3 downto 0);
rot_a: in std_logic;
rot_b: in std_logic;
rot_center: in std_logic;
RS232_DCE_TXD: out std_logic

);
end FunctionGen ;

--------------------------------------

architecture Behavior of FunctionGen is

signal INDEX: std_logic_vector(7 downto 0);
signal ASCII: std_logic_vector(7 downto 0);
--signal BinIN: std_logic_vector (15 downto 0);
--signal BcdOut: std_logic_vector (19 downto 0) );
signal sBCDin: std_logic_vector (15 downto 0);
signal sBCDout: std_logic_vector (19 downto 0);
signal start : std_logic;

signal Rotarydata: std_logic_vector(11 downto 0);
signal bit12 : std_logic_vector (11 downto 0);
signal divider: std_logic_vector(31 downto 0);
signal full: std_logic;
signal khz: std_logic;
signal AdcA_data: std_logic_vector(13 downto 0);

begin

LED<=AdcA_data(13 downto 6);
--LED<=bit12(11 downto 4);
--------------- Initializing ------------------------
SPI_SS_B <= '1';
SF_CE0 <= '1';
FPGA_INIT_B <= '1';
-----------------------------------------------------



sBcdIn <= b"00" & AdcA_data;

pBinBcd: Bin16_Bcd5 port map (Clk => CLK,
BinIN => sBcdIn,
BcdOut => sBcdOut );



--------------------------- LCD DRIVER ---------------------------
pLcd: LCD_DRIVER
port map(Clk => CLK,
rs => LCD_RS,
rw => LCD_RW,
enable => LCD_E,
lcd_data => SF_D,

index => INDEX,
char => ASCII);
---------------- connecting DAC ---------------------
pDAC: S3E_AnalogIO port map
( Clk => Clk,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO,
SPI_SCK => SPI_SCK,
DAC_CS => DAC_CS,
DAC_Clr =>DAC_Clr,
AMP_CS => AMP_CS,
AD_CONV => AD_CONV,
-- locals
--TickAnalogIO => open,
Dac_A => bit12,
--Dac_B => not bit12, --open,
--Dac_C => open,
Dac_D => Rotarydata,

Adc_A => AdcA_Data
--Adc_B => open

);

cRot: Rotary_Counter
generic map (bits => 12)
Port map (clk => clk,
Rot_a => Rot_a,
Rot_b => Rot_b,
Rot_center => Rot_center,
COUNTER => Rotarydata
);

cSerial: Comp_RS232_TX
Port map
(clk => clk,
sDout => RS232_DCE_TXD,
Data => AdcA_data(13 downto 6),
start => Khz
);


------------------ 1Khz counter ---------------------
pDiv: process(clk)
begin
if rising_edge(clk) then
if divider<100000 then ------ 500 hz

divider<= divider+1;
khz<='0';
else
divider<=(others=>'0');
khz<='1';
end if;
end if;
end process;
-----------------------------------------------------
---------------- 12 bit counter ---------------------
p12bit: process(clk)
begin

if rising_edge(clk) then
if khz='1' then
if full='0' then
bit12 <= bit12 + sw; ---- if +sw put x"ff0"
if bit12 > x"ff0" then
full<='1';
end if;
end if;
if full='1' then
bit12<= bit12 - sw; ---- if -sw put x"00F"
if bit12 < x"00f" then
full<='0';
end if;
end if;

end if;
end if;
end process;
------------------------------------------------------
------------ initialize LCD -------------
SF_CE0<='1';
-----------------------------------------
----------------- Display Time and name --------------
with INDEX select
ASCII <= x"00" when x"00",
x"41" when x"01",
x"44" when x"02",
x"43" when x"03",
x"3D" when x"04",
x"00" when x"05",
x"00" when x"06",
x"3" & sBCDout(19 downto 16) when x"07",
x"3" & sBCDout(15 downto 12) when x"08",
x"3" & sBCDout(11 downto 8 ) when x"09",
x"3" & sBCDout(7 downto 4) when x"0A",
x"3" & sBCDout(3 downto 0) when x"0B",
x"00" when others;
------------------------------------------------------------------
end Behavior;

to download the project please click here
https://rapidshare.com/files/2030142705/DAC_VHDL.rar